MATLAB TARGET SUPPORT PACKAGE 4 - FOR USE WITH TEXAS INSTRUMENTS C6000 Uživatelský manuál stáhnout pdf (Strana 4)

Chapter 7 Hardware Implementation Tools

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 Eight 32-Bit Instructions/Cycle

 32/64-Bit Data Word

 300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock

Rates

 3.3-, 4.4-, 5-, 6-Instruction Cycle Times

 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS

 Rich Peripheral Set, Optimized for Audio

 Highly Optimized C/C++ Compiler

 Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core

 Eight Independent Functional Units:

o 2 ALUs (Fixed-Point)

o 4 ALUs (Floating-/Fixed-Point)

o 2 Multipliers (Floating-/Fixed-Point)

 Load-Store Architecture with 32 32-Bit General-Purpose Registers

 Instruction Packing Reduces Code Size

 All Instructions Conditional

 Instruction Set Features

 Native Instructions for IEEE 754: Single and Double precision

 Byte-Addressable (8-, 16-, 32-Bit Data)

 8-Bit Overflow Protection

 Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization

 L1/L2 Memory Architecture

 4K-Byte L1P Program Cache (Direct-Mapped)

 4K-Byte L1D Data Cache (2-Way)

 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and

192K-Byte Additional L2 Mapped RAM

 Device Configuration

 Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

 Endianness: Little Endian, Big Endian

 32-Bit External Memory Interface (EMIF)

 Glue less Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM

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MATLAB TARGET SUPPORT PACKAGE 4 - FOR USE WITH TEXAS INSTRUMENTS C6000 Uživatelský manuál Strana 4