Chapter 7 Hardware Implementation Tools
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Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache
(L2) consists of a 256K-byte memory space that is shared between program and data space. 64K
bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or
combinations of the two. The remaining 192K bytes in L2 serve as mapped SRAM.
The C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports
(McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I
2
C)
buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers,
a host-port interface (HPI), and a glue less external memory interface (EMIF) capable of
interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface
modules each support one transmit and one receive clock zone. Each of the McASP has eight
serial data pins, which can be individually allocated, to any of the two zones. The serial port
supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has
sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial
data in each zone may be transmitted and received on multiple serial data pins simultaneously
and formatted in a multitude of variations on the Philips Inter-IC Sound (I
2
S) format. In
addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958,
AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full
implementation of user data and channel status fields. The McASP also provides extensive error
checking and recovery features, such as the bad clock detection circuit for each high-frequency
master clock, which verifies that the master clock is within a programmed frequency range. The
two I
2
C ports on the TMS320C6713 allow the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel-buffered serial port
(McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral
devices.
The TMS320C6713 device has two boot modes: from the HPI or from external
asynchronous ROM. The TMS320C67x DSP generation is supported by the TI eXpressDSP -
set of industry benchmark development tools, including a highly optimizing C/C++ Compiler,
the Code Composer Studio - Integrated Development Environment (IDE), JTAG-based
emulation and real-time debugging, and the DSP/BIOS kernel.
7.1.1 DSP 6713 Features
Highest-Performance Floating-Point Digital Signal Processor (DSP):
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