MATLAB EMBEDDED IDE LINK 4 Uživatelská příručka

Procházejte online nebo si stáhněte Uživatelská příručka pro Video převodníky MATLAB EMBEDDED IDE LINK 4. MATLAB EMBEDDED IDE LINK 4 User`s guide Uživatelská příručka

  • Stažení
  • Přidat do mých příruček
  • Tisk

Shrnutí obsahu

Strany 1 - Evaluation of a DSP for

Industrial Electrical Engineering and Automation CODEN:LUTEDX/(TEIE-5259)/1-57/(2008)Evaluation of a DSP for power electronic applications Per Moli

Strany 2

8Each event manager is equipped with two independent timers – making it a total of four. Timers are useful when handling time critical algorithms or

Strany 3 - Acknowledgements

94 - Software A number of software tools has been used and evaluated for this report, giving the user two main alternatives when programming – eith

Strany 4 - Table of contents

10 Screenshot of CCS 3.1 CCS v3.1 comes with a selection of emulators, including a F2812 specific. This is a great feature considering that the hard

Strany 5

115 - Implementation of a digital relaying algorithm 5.1 – Relays of the past and present Since the beginning of the 20th century, relays built wi

Strany 6 - 1.1 - Outline of the report

125.2 – The model To check the suitability of the DSP regarding power electronic applications, a simplified relay model is constructed. The model co

Strany 7 - 2.1 – Areas of interest

136 - Benchmark Considering that relays and circuit breakers demand short response times between the actual error and the moment when the signal ha

Strany 8 - 2.2 – The verdict

14The system clock frequency of 150MHz is divided by the high speed clock prescaler of 2, and then divided by the timer control input clock prescaler

Strany 9 - 3 - Hardware

157 - Conclusion As shown in previous chapters the F2812 performs really well in this type of applications, and the Link- and Target- package for S

Strany 10

168 - References 8.1 – Books [8.1.1] Computer Relaying for Power Systems, Arun G. Phadke, James S. Thorp, SRP Ltd., 2000 [8.1.2] Power System A

Strany 11 - 4 - Software

17Appendix A – A Quick guide to CCS and the hardware A.1 – Before you start Basic experience of c/c+ is highly recommended. Download the example

Strany 12

Evaluation of a DSP for power electronic applications Master Thesis work, 2008 at The Department of Industrial Electrical Engineering and Aut

Strany 13

18A.2 - Code Composer Studio A.2.1 – The User Interface Directly after opening CCS, your screen should look something like this: Let’s start by

Strany 14 - 5.2 – The model

19In this case, we open up the project Example_281xEvPwm.pjt. Note that we have a beautifully arranged directory-style file structure with the main

Strany 15 - 6 - Benchmark

20enabled. (this procedure can also be used for the removal of breakpoints) To review the deployed breakpoints a command called simply “Breakpoints”

Strany 16

21A.3 - Hardware Note that a lot of the information found in this section only applies for the modified F2812 with interface card. On the front pla

Strany 17 - 7 - Conclusion

22 The DSP-board A.3.1 – The LEDs The LEDs are connected to the P7-connection on the DSP-board. Here’s a code segment displaying how to use them:

Strany 18 - 8 - References

23A.3.2 – The buttons The buttons are also connected to the P7-connection and can be used in the following manner: void Init_Buttons(void){ EALLOW;

Strany 19 - A.1 – Before you start

24 A.3.4 – Rear connections The DSP can generate a pulse train with variable period (actually, its duty cycle) - this method, PWM (Pulse-Width Modula

Strany 20 - A.2 - Code Composer Studio

25 // Initalize EVA Timer2 EvaRegs.T2PR = 0x03FF; // Timer2 period EvaRegs.T2CMPR = 0x03C0; // Timer2 compare EvaRegs.T2CNT = 0x0000;

Strany 21 - A.2.2 Compiling

26This concludes the CCS part of the guide, please refer to the literature used in this report for further information.

Strany 22

27Appendix B – Simulink blocks This part of the guide covers some of the new Simulink blocks and how to use them. Basic knowledge of Simulink and M

Strany 23 - A.3 - Hardware

1Acknowledgements The author would like to thank Magnus Akke and Gunnar Lindstedt for their invaluable support and expertise during this project.

Strany 24 - A.3.1 – The LEDs

28 A lot of options regarding the control logic and deadband are also available – giving the user full control over how the resulting signal shoul

Strany 25 - A.3.2 – The buttons

29 Nonetheless, it has great potential and a closer look at the example programs provided by Mathworks is highly recommended. Finally, some old a

Strany 26 - A.3.4 – Rear connections

30Appendix C – Useful registers The contents of this chapter should be of little interest when using Simulink to generate the code. Should one ever

Strany 27

31Another useful register is GPTCONA (Address 7400h) GPTCONA as seen in the Event Manager Reference Guide Bit(s) Name Description 15 Rese

Strany 28

32Bit(s) Name Description 4−3 Reserved 2 C3TRIPE C3TRIP Enable: 1 C2TRIPE C2TRIP Enable: COMCONA contains settings for the PWM

Strany 29 - Appendix B – Simulink blocks

33 ADCTRL1 as seen in the Analog-to-Digital Converter Reference Guide Bit(s) Name Description 15 Reserved Reads return a zero. Writes h

Strany 30

34Appendix D – Simulink Models D.1 – The relay algorithm This is the main model, notice the ADC block in red, the green Digital Output block con

Strany 31

35 The contents of the oscillator subsystem. A 50 Hz reference signal is on the input side – sine- and cosine-waves are outputted. D.2 – The benchm

Strany 32

36 The first triggered subsystem, triggered by the push of a button – the current timer position is read and saved – the filter calculation is starte

Strany 33

37Appendix E – C-code E.1 – The relay algorithm Code Composer Studio generates all necessary files and directories, I’ve chosen to only include th

Strany 34

2Table of contents TABLE OF CONTENTS...

Strany 35

38 /* S-Function Block: <Root>/ADC (c28xadc) */ { AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;// Sequencer reset AdcRegs.ADCTRL2.bit.SOC_SEQ

Strany 36 - Appendix D – Simulink Models

39 */ rtb_Gain.re = TwinDFTs_CCS_P.Gain_Gain_n * rtb_ComplextoMagnitudeAngle1_o2; rtb_Gain.im = TwinDFTs_CCS_P.Gain_Gain_n * rtb_PhaseRelay;

Strany 37 - D.2 – The benchmark model

40 */ rtb_Product.re = TwinDFTs_CCS_P.Gain_Gain_m * rtb_Angle; rtb_Product.im = TwinDFTs_CCS_P.Gain_Gain_m * rtb_PhaseRelay; /* ComplexToMag

Strany 38

41 TwinDFTs_CCS_B.TmpHiddenBufferAtDigitalOutputI[0] = rtb_RelayDFT1; TwinDFTs_CCS_B.TmpHiddenBufferAtDigitalOutputI[1] = rtb_RelayDFT2; TwinDFT

Strany 39 - Appendix E – C-code

42static void TwinDFTs_CCS_update(int_T tid) { /* Update for UnitDelay: '<S7>/Unit Delay' */ TwinDFTs_CCS_DWork.UnitDelay_DSTATE

Strany 40

43 /* Update absolute time for base rate */ if (!(++TwinDFTs_CCS_M->Timing.clockTick0)) ++TwinDFTs_CCS_M->Timing.clockTickH0; TwinDFT

Strany 41

44 pVoidBlockIORegion = (void *)(&TwinDFTs_CCS_B.ADC[0]); for (i = 0; i < 13; i++) { ((real_T*)pVoidBlockIORegion)[i] = 0.0;

Strany 42

45 void MdlInitialize(void) { /* InitializeConditions for UnitDelay: '<S7>/Unit Delay' */ TwinDFTs_CCS_DWork.UnitDelay_DSTATE = T

Strany 43

46 * o Embedded Target for TI C6000 DSP User's Guide */ #include "TwinDFTs_CCS.h" #include "TwinDFTs_CCS_private.h" #inc

Strany 44

47// Entry point into the code // void main(void) { volatile boolean_T noErr; const char_T *status; init_board(); /************************

Strany 45

3A.3 - HARDWARE... 21

Strany 46

48 */ #include "TwinDFTs_CCS.h" #include "TwinDFTs_CCS_private.h" /* Block parameters (auto storage) */ Parameters_TwinDFTs_CCS

Strany 47 - E.1.2 – TwinDFTs_CCS_main.c

49 { -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0, -0.0 }, /* Meanof20samples1

Strany 48

50 #include "benchmark.h" #include "benchmark_private.h" /* Block signals (auto storage) */ BlockIO_benchmark benchmark_B; /* B

Strany 49 - E.1.3 – TwinDFTs_CCS_data.c

51 { int_T i; const real_T *Amtx = &benchmark_P.DiscreteFilter_A[0]; real_T *x = &benchmark_DWork.DiscreteFilter_DSTATE[

Strany 50

52 /* Initialize timing info */ { int_T *mdlTsMap = benchmark_M->Timing.sampleTimeTaskIDArray; mdlTsMap[0] = 0; benchmark_M->Ti

Strany 51 - E.2 – The benchmark model

53/* Model terminate function */ void benchmark_terminate(void) { /* (no terminate code required) */ } /*=========================================

Strany 52

54void MdlTerminate(void) { benchmark_terminate(); } /*========================================================================* * End of GRT com

Strany 53

55 * is what makes the generated code "real-time". The function rt_OneStep is * always associated with the base rate of the model. Subra

Strany 54

56 rtmGetOffsetTimePtr(S), rtmGetSampleHitPtr(S), rtmGetSampleTimeTaskIDPtr(S), rtmGetTStart(S), &rtmGetSimTimeStep(S), &a

Strany 55

41 - Introduction and project outline The complexity of the power grid increases with its continuous expansion and the addition of software control

Strany 56 - E.2.2 – benchmark_main.c

52 - Alternatives and their properties Before choosing the system to be evaluated, four main DSP-alternatives have been scrutinized in order to fin

Strany 57

62.1.3 - Signal levels Regarding signal levels, the eZdsp is the only alternative that doesn’t support the standardized [-10, 10] V by default – howe

Strany 58 - E.2.3 – benchmark_data.c

73 - Hardware In the previous chapter the decision to evaluate the Spectrum Digital eZdsp F2812 was made. The obvious reasons for choosing the eZ

Komentáře k této Příručce

Žádné komentáře